Cadence 75 Marks Paper Time Limit 1.15 H Technical Part 1. Ans: O (n**2) 2. In order & preorder seq. of tree is given & you have to find out post order.. very easy but do practice you can make one easy method by practice.. 3. problem on pass by ref. & pass by value. [...]
VSNL Design Test Paper Pattern VSNL Design test Which phase is important for design verification? – Design – Planning – Implementation – Building Answer d Match each methodology step in the lettered list with the correct procedure description in the numbered list extracting customer requirements characterizing the existing network designing topology and network solutions building [...]
VERITAS Sample Paper & Pattern 24th July, 2000 IN IIT BOMBAY It was a 1 hr test. 100 marks! *Section 1 20 questions objective, negative marking ( 2 correct, -1 incorrect ) *What is TLB? (meaning translation lookaside buffer) *Which cannot be swapped from a system which uses only tape as the backup store? -page [...]
